1. Field of the Invention
The present invention relates to a bus communication architecture, more particularly, the present invention relates to serializing a parallel bus interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer in an ATM system.
2. Art Background
ATM is a network protocol and switch-based method of communication which breaks down a communication process into several sub processes arranged in a stack. Each layer of the protocol stack provides services to the layer above it which allows the top most processes to communicate. Each layer communicates with another layer over defined interfaces enabling two different devices, using hardware and software from different manufacturers, but still conforming to the ATM model, to communicate over an ATM network. Using ATM, information sent over a network is segmented into a fixed length cell. The ATM cell has a fixed length of 53 bytes comprising 5 bytes of header information and 48 bytes of data information (e.g. voice, data, or video information).
Two layers in the protocol stack are the asynchronous transfer mode (ATM) layer and the physical (PHY) layer. The PHY layer interfaces directly to network media (e.g. fiber optics, twisted pair, etc.) and also handles transmission convergence (extracting ATM cells from the transport encoding scheme). The ATM layer and the PHY layer communicate over a parallel bus termed the Universal Test and Operations PHY Interface for ATM (UTOPIA) developed by the ATM forum. The UTOPIA bus is a bidirectional bus which transmits and receives ATM cells simultaneously. The UTOPIA bus is defined to support numerous transmission rates defined for ATM, including transmission rates as high as 622 Mbps. The UTOPIA bus defines two interface signal groups: Transmit and Receive. As illustrated in FIG. 1a, the Transmit interface 16 moves data information from ATM layer 12 to PHY layer 14, while the Receive interface 18 moves information from ATM layer 12 to PHY layer 14.
As illustrated in FIG. 1b, the Transmit interface comprises a parallel transmit data bus TxData 20 which may be, for example, 8-bits or 16-bits wide, and a number of control signals which may be utilized in the Octet Level Handshaking (OLH) mode or the Cell Level Handshaking (CLH) mode. In CLH mode data is moved between ATM layer 12 and PHY layer 14 as an entire uninterrupted cell. The transmit control signals include: transmit enable signal TxEnb* 22 which when asserted low by ATM layer 12 indicates that TxData 20 contains valid cell data; transmit start of cell signal TxSOC 24 which is asserted high by ATM layer 12 when TxData 20 contains the first valid byte of cell data; transmit full/cell available signal TxFull*/TxClav 26 which in CLH mode is asserted high by PHY layer 14 when it can accept a full cell of data, and is asserted low by PHY layer 14 when it is xe2x80x9cfullxe2x80x9d and cannot accept a full cell of data; and transmit clock signal TxClk 28 which is provided by ATM layer 12 for synchronization of the data transfer from ATM layer 12 to PHY layer 14.
Transmitting data from ATM layer 12 to PHY layer 14 in the CLH mode of operation is generally as follows. PHY layer 14 indicates to ATM layer 12 that it can accept a complete cell of data (53 bytes) by asserting TxFull*/TxClav to a high logic level. When ATM layer 12 has a complete cell to transfer to PHY layer 14, it asserts TxEnb* to a low logic level and places the first byte of data onto data bus TxData 20. Additionally, ATM layer 12 asserts TxSOC 24 to a high logic level along with the first byte of data. TxSOC 24 remains at a high logic level for the first cycle only. Each of the remaining 52 bytes of cell data are then transferred to PHY layer 14 at one byte per dock cycle of TxClk 28.
In like manner, FIG. 1b also illustrates the Receive interface comprising a parallel receive bus RxData 30 which may be, for example, 8-bits or 16 bits wide, and a number of control signals similar to the those described with respect to the Transmit interface. The receive control signals include: receive enable signal RxEnb* 32 which when asserted low by ATM layer 12 indicates that RxSOC 34 is valid and that RxData contains valid data; receive start of cell signal RxSOC 34 which is asserted by PHY layer 14 when RxData 30 contains the first valid byte of cell data; receive empty/cell available signal RxEmpty*/RxClav 36 which in CLH mode is asserted high by PHY layer 14 when it has a full cell of data to send to ATM layer 12, and is asserted low by PHY layer 14 when it is xe2x80x9cemptyxe2x80x9d and does not have a full cell of data to send to ATM layer 12; and receive clock signal RxClk 38 which is provided by ATM layer 12 for synchronization of the data transfer from PHY layer 14 to ATM layer 12.
Receiving data from PHY layer 14 at ATM layer 12 in the CLH mode of operation is generally as follows. PHY layer 14 indicates to ATM layer 12 that it has a complete cell of data (53 bytes) to send by asserting RxEmpty*/RxClav to a high logic level. When ATM layer 12 can receive a complete cell, it asserts RxEnb* to a low logic level. In the next clock cycle, PHY layer 14 places the first byte of data onto the data bus RxData 30 and asserts RxSOC 34 to a high logic level along with the first byte of data. RxSOC 34 remains at a high logic level for one cycle only. Each of the remaining 52 bytes of cell data are then transferred to ATM layer 12 at one byte per clock cycle of RxClk 38.
Typical applications using UTOPIA include Network Interface Cards (NICs) and ATM switches. ATM switches typically are built using a rack mounted architecture which include individual shelves supporting PHY layer circuits or ATM layer circuits. Typically, the interconnect between the PHY layer circuits and the ATM layer circuits comprise wide parallel ribbon cables. The parallel ribbon cables may comprise as many as 40 conductors to accommodate the Transmit and Receive interfaces when the UTOPIA bus operates in a 16-bit mode. The use of wide ribbon cables to interconnect the ATM layer circuits and PHY layer circuits physically clutters the ATM switch. Additionally, the wide parallel ribbon cables connecting the various UTOPIA ports on a switch can extend to as much as a foot or more in length, depending on the distance between the PHY and ATM layer circuit shelves. The length of the ribbon cable poses a limitation on the ATM system as parallel ribbon cables, which operate reliably at one frequency over a given distance, may not operate reliably if that distance is increased.
UTOPIA ports generally operate at high frequencies (e.g. 25 MHz). Appreciably long ribbon cables operating at high speeds introduce undesirable problems such as cross-talk between conductors and voltage reflections due to the uncontrolled impedance of the ribbon cable. These problems cause degradation of signal integrity and skew problems in which the timing relationships of the signals transmitted between the ATM layer and the PHY layer are altered. Skew problems can result in the violation of set-up and hold timing parameters resulting in corruption of data.
One approach to address the signal integrity and skew problem is to employ specialized ribbon cable for transmitting differential signals, such as twisted pair conductors. However, this approach does not resolve the skew problem since skew can still result from differences in propagation delays for each signal through its respective differential driver, cable and receiver. Additionally, this approach doubles the number of conductors required for the parallel cable because each signal requires two conductors. Thus the already bulky ribbon cable further clutters the area between the ATM and PHY layer circuits.
Another approach is to use ribbon cables interconnected with repeater circuits. The repeater circuits would operate as a bridge to reliably increase the effective length of the ribbon cable. However, this approach also compounds the problem of cluttering the space around the ATM switch, as well as, significantly increasing the cost of the system as the effective length of the ribbon cable grows.
Thus, what is needed is a method and apparatus for implementing the parallel architecture of the UTOPIA bus which does not have undesirable effects, such as, degrading signal integrity, creating timing skew problems, encountering physical space constraints, or employing high cost solutions. Additionally, what is needed is a method and apparatus for extending the distance over which ATM and PHY layer circuits may reliably operate.
A novel method and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer is disclosed.
In one embodiment of the present invention, an extender circuit is disclosed. The extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit for communicating in parallel with the ATM layer, and the second circuit for communicating in parallel with the PHY layer. The extender circuit additionally includes a serial link which serially transmits signals between the first and second circuits. The serial link may comprise a first serial link for transmitting a first serial signal from the first circuit to the second circuit, and a second serial link transmitting a second serial signal from the second circuit to the first circuit.
The first circuit and the second circuit comprise similar architecture. The first circuit comprises a parallel interface circuit for communicating in parallel with the ATM layer and a serial interface circuit coupled to the parallel interface circuit for serially communicating with the second circuit. The parallel interface circuit may comprise control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit may comprise serializing/deserializing circuitry which comprises serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and for outputting a plurality of serial output signals. The serializing/deserializing circuitry further comprises deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals which are provided to the parallel interface circuit.
In another embodiment of the present invention, an interface circuit for interfacing an ATM layer to a serial bus is described. The serial bus is operative to be coupled to a PHY layer. The interface circuit includes a parallel interface circuit communicating in parallel with the ATM layer, and a serial interface circuit coupled to the parallel interface circuit and serially coupled to the serial bus. The parallel interface circuit comprises control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit may comprise serializing/deserializing circuitry which comprises serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and for outputting a plurality of serial output signals. The serializing/deserializing circuitry further comprises deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals which are provided to the parallel interface circuit.
In another embodiment of the present invention, an interface circuit for interfacing a PHY layer to a serial bus is described. The serial bus is operative to be coupled to an ATM layer. The interface circuit includes a parallel interface circuit communicating in parallel with the PHY layer, and a serial interface circuit coupled to the parallel interface circuit and serially coupled to the serial bus. The parallel interface circuit comprises control circuitry, such as a programmable logic device, and memory circuitry, such as a first-in-first-out (FIFO) memory device. The serial interface circuit may comprise serializing/deserializing circuitry which comprises serializing circuitry for serializing a plurality of parallel signals received from the parallel interface circuit and for outputting a plurality of serial output signals. The serializing/deserializing circuitry further comprises deserializing circuitry for deserializing a plurality of serial input signals to form a plurality of deserialized signals which are provided to the parallel interface circuit.
In another embodiment of the present invention, a novel method is described for serially transmitting a plurality of signals between an ATM layer and a PHY layer via an extender circuit. The method comprises: generating a first plurality of parallel signals; serializing the first plurality of parallel signals to form a first plurality of serial signals; transmitting the first plurality of serial signals between the ATM layer and the PHY layer; and deserializing the first plurality of serial signals to form a second plurality of parallel signals. The second plurality of parallel signals are equivalent to the first plurality of parallel signals. The extender circuit includes a memory circuit for storing the second plurality of parallel signals. The method further provides the second plurality of parallel signals to the memory circuit and outputs the second plurality of parallel signals from the memory circuit. A first flag condition is signaled when the memory circuit contains a first predetermined number of the second plurality of parallel signals. A first control code is generated in response to the memory circuit signaling the first flag condition. The first control code is serialized to form a first serialized control code which is transmitted between the ATM layer and the PHY layer. The first control signal disables the transmission of the first plurality of signals between the ATM layer and the PHY layer. A second flag condition is signaled when the memory circuit contains a second predetermined number of the second plurality of parallel signals. A second control code is generated in response to the memory circuit signaling the second flag condition. The second control code is serialied to form a second serialized control code which is transmitted between the ATM layer and the PHY layer. The second control signal enables the transmission of the first plurality of data signals between the ATM layer and the PHY layer.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.